Sparsh Mittal
Assistant
Professor (and IEEE senior member)
Department
of Electronics and Communications Engineering
Joint
faculty at Mehta Family School of Data Science and Artificial Intelligence
Indian
Institute of Technology, Roorkee, India.
Email: sparsh0mittal at gmail dot com;
sparshfec at iitr.ac.in (which is an alias of sparsh.mittal at ece.iitr.ac.in and sparsh.mittal at mfs.iitr.ac.in)
Profiles at Google
Scholar, Academia.edu,
ResearchGate, LinkedIn, PublicationsList
and ACM-Library
. ORCID: 0000-0002-2908-993X
Webpage of CANDLE
research lab
My talks on improving
clarity in paper-writing, making
technical figures, writing survey
papers and making presentations.
Research Interests
Processor architectures for machine learning,
neural network accelerators, autonomous driving vehicles, computer architecture
(CPUs and GPUs), VLSI, high-performance computing, approximate computing.
Awards and Honors
1.
In the Stanford's list of world's top researchers 2021, in the
field of Computer Hardware & Architecture, I am ranked as number 71 (for
whole career) and as number 3 (for year 2020). In 2020 list, I was ranked 107
(for whole career) and as number 3 (for year 2019 alone).
2.
My research on mobile-phone usage detection was praised by
Education Minister of India (1, 2, 3).
It was covered by TOI,
HinduBusinessLine, TelanganaToday, Andhrajyothi
and many other media platforms.
3.
My research has been covered by several technical news websites,
e.g. Phys.org,
TheMemoryGuy, InsideHPC (1,
2,
3, 4,
5,
6,
7,
8), Primeur
Magazine, StorageSearch 1, StorageSearch
2, StorageSearch
3, Data-Compression.info,
TechEnablement, ScientificComputing, SemiEngineering (semiconductor engineering), ReRAM
forum and HPCWire (1,
2,
3,
4,
5).
4.
My opinion-articles in popular media: BusinessWorldEducation, Eduvoice
5.
My application for recruiting a student on Intel PhD fellowship
2018 was approved.
6.
Received Distinguished
Contribution rating at ORNL
based on 2013-2014 performance appraisal. This rating recognizes the top 10
percent of staff.
7.
Received Outstanding
Contribution rating at ORNL
based on 2014-2015 performance appraisal. Also received a performance award.
8.
Gave an invited presentation at Memory
for HPC Systems session at ISC,
Germany 2016. ISC is a top conference with 3000 attendees and bi-annual Top500
list is announced here.
9.
Best student paper candidate in SC 2014
10.
ECpE fellowship from
Electrical and Computer Engineering Department, Iowa State University, USA of
$2500 in 2008.
11.
Peer Research Award from Iowa State University, USA of $200 in
2013.
12.
Topper in Electronics batch of year 2008 in ECE department at IIT
Roorkee and received Institute Silver Medal for this.
13.
Institute Silver Medal for Best B.Tech project award in Electronics and Computer
Engineering (ECE) Department at IIT Roorkee.
14.
Sumer Chand Jain Scholarship of INR 10,000 from IIT Roorkee.
15.
Best Student Award from High School (named MHS, Jaipur, Rajasthan,
India) in 2004. Topper throughout school
Selected Publications
CORIDOR: Mitigating
read-disturbance in STT-RAM: ACM
TECS 2021
Multi-level MRAM cells IEEE
TED and IOP SST 2021
A pruning technique for CNNs JSA
2021
Side-channel attacks to leak
architecture of compact DNN ACM
JETC 2020 and leak layer-types of a CNN on CPU AIMLSystems 2021
Modeling data-reuse in DNNs IEEE
Trans. on Computers 2020
Deep-learning for detecting
mobile usage GOODTECHS
2020
Improving accuracy of object
detection algorithms using Multiscale Feature Aggregation Plugins ANNPR
2020
Co-Optimizing Hardware
Utilization, and Performance of DNNs on Systolic Accelerator: ISVLSI
2020
Subspace attention module for
compact DNNs: WACV
2020
Energy-efficient group
convolution in DNNs: VLSID
2020
Approximate Load Value Prediction
in GPUs: ICS
2019
Ramifications of making DNNs
compact: VLSID
2019
NVM-based Swapping Framework for
Guest OSes in VMs: IEEE
Access 2017
Designing SOT-RAM based GPU
register file: ISVLSI
2017
Addressing read-disturbance issue
in STT-RAM cache: CAL
2017 (1)
Addressing write-disturbance
issue in PCM memory: CAL
2017 (2)
Improving soft-error reliability
of GPU register file: VLSID
2017
Inductive charge pump for 3D
stacked PCM: GLSVLSI
2017
Write overhead management in NVM
caches and main memory: HPDC
2016, IEEE
TVLSI 2016, IEEE
CAL 2015, IEEE
MASCOTS 2015, GLSVLSI
2014, ISVLSI
2014, USENIX
INFLOW 2014
Power management in SRAM and eDRAM caches: HPDC
2014, IEEE
TVLSI 2013, ICCD
2013, VLSID
2013
Improving soft-error reliability
of SRAM caches: GLSVLSI
2016
Application resiliency modeling
and metric: SC
2014
Survey papers:
Machine learning/deep learning
Approximate
computing and storage (summary
PPT)
Deep
learning for vehicle detection from UAV images
FPGA-based
accelerators for CNNs, Deep
learning accelerators on NVIDIA Jetson, FPGA/GPU/ASIC
accelerators for RNNs, Accelerators
for 3D CNNs, Hardware
accelerators for GANs (generative adversarial networks)
Deep
Learning on GPUs , Reliability
of deep-learning algorithms and accelerators
Deep
Learning on CPUs, Hardware
security of DNN models and accelerators
Memristor
(ReRAM) based and Spintronic-based
architectures for Processing-in-memory and Neural networks (summary
PPT)
System-level
On CPU-GPU
heterogeneous computing
On big.LITTLE-style asymmetric multicore processors (for
example, Samsung's Exynos 5 Octa)
(summary
PPT)
On Micron’s
Automata Processor
On intermittent
computing systems
On
comparison between energy
efficiency of GPUs, FPGAs and CPUs
Networking
and architectural techniques for mobile
web browsing
System component-level: architectural techniques for
GPU
register file (summary
PPT) and GPU
caches
TLBs
(translation lookaside buffer) (summary
PPT)
Value
prediction and value locality
Architectural Management Techniques For
Cache
partitioning in multicore processors (summary
PPT)
Power
management of GPUs,
data
centers, embedded
systems, SRAM
caches, DRAM
main memory and PCM
main memory
Near-threshold
computing (summary
PPT)
Data
compression in cache and main memory (summary
PPT)
Soft-error
resilience for CPUs and GPUs (summary
PPT)
Managing
process variation in CPUs and GPUs (summary
PPT)
Addressing
soft-error issues in non-volatile memories (summary
PPT)
Reliability
techniques for DRAM
Encoding
techniques for reducing data-movement energy
Cache
bypassing in CPUs, GPUs and CPU-GPU systems and SRAM, NVM and stacked-DRAM
caches (summary
PPT)
On security techniques for:
Non-volatile
memories and GPUs
On memory technologies:
Stacked-DRAM
caches (summary
PPT), eDRAM and NVM caches, domain
wall memory (racetrack memory) (summary
PPT)
NVMs
(e.g. Flash) for storage systems and main memory
SLC/MLC/TLC
Hybrid Flash Memory based SSDs
On question
answering systems (natural language processing)
See http://publicationslist.org/sparsh0mittal for full publication list and download links.
The
PowerPoint slides of a few conference presentations are available here. Summaries of
survey papers can be obtained by clicking on summary PPT above.
Funded Proposals
2017/04:
SERB early career research (ECR) award, title: Secure and Reliable Non-volatile Memories for Ultra-low
Power Applications
2018/08:
SRC USA, title: Designing efficient hardware-accelerators for Autonomous
Driving Vehicles
Open-source software released
1.
DESTINY:
DESTINY is an acronym for 3D design-space exploration
tool for SRAM, eDRAM and non-volatile memory.
DESTINY can model:
* (2D/3D) SRAM and eDRAM
* (2D/3D, SLC/MLC) STT-RAM, ReRAM and PCM
* (2D, SLC/MLC) SOT-RAM, Flash, DWM
In its purpose, DESTINY is similar to CACTI, CACTI-3DD or
NVSim. Here are manual
and the JLPEA 2017 journal
paper. Source-code is available here. See its news
coverage on ReRAM
forum.
The proverb goes, write
your own destiny. Hence, we have
written our own [tool named] DESTINY. J
2.
Code and trained model of our
WACV-2020 paper ULSAM: Ultra-Lightweight
Subspace Attention Module for Compact Convolutional Neural Networks
3.
Code and trained model of
our VLSID-2020 paper E2GC:
Energy-efficient Group Convolution in Deep Neural Networks
4.
Dataset and
trained models of our GOODTECHS-2020 paper Detecting Usage of Mobile Phones using Deep Learning Technique
5.
Both serial and parallel versions
of code of red-black SOR (successive over-relaxation) method in three
state-of-the-art languages, viz. Chapel (from Cray Inc.), D (also called dlang, from Digital Mars) and Go (also called golang, from Google) can be downloaded for academic use
from this
link. They were used in this
paper. Chapel version of the code has been incorporated in Chapel performance
test suite/examples.
Invited Presentations/Seminars
* Xilinx, Hyderabad, 2019/07
* Intel India Research Colloquium
2017/10 (Bangalore)
* VelTech
University, Chennai, India 2017
* PARCOMPTECH,
Bangalore, India 2017 (organized by CDAC and DeitY)
* ISC Conference, Germany, 2016/06 (link)
* University of Michigan, 2015/11
* New York University 2016/02
Professional Background
Postdoctoral
research associate at Oak Ridge National Lab, USA (2013-2016)
PhD
from Iowa State University (ISU), Ames, Iowa, USA (2008-2013).
BTech from
Indian Institute of Technology (IIT) Roorkee, Uttarakhand, India (2004-2008).
Outreach
2018-03-08:
A TLC workshop on Computer Organization,
held at Anurag Group of Institutions, Ghatkesar
2017-11-10:
On Advanced Computer Architecture,
held at MITAOE (Pune, India)
2017-08-11:
A TLC workshop on Computer Architecture,
held at Anurag Group of Institutions, Ghatkesar
2017-03-04:
A TLC workshop on Advanced Memory System
Architecture, held at IIT Hyderabad
Professional Activity
Associate editor of Journal of Systems
Architecture
Reviewer for:
Reviewed proposals for three European
research-funding agencies.
TPC member of: VLSID 2020
ACM: Computing Surveys (3 times), TACO
(2 times), TECS (2 times)
IEEE: TNNLS 2021, TAI 2020, TETC 2018,
DATE 2018, DFT 2016, CAL (3 times), Intelligent Systems, ISVLSI, JETCAS, Trans.
on Computers (2 times), Trans. On VLSI Systems, TCAD (2 times), DFT, HiPC student research symposium
Springer: Cluster Computing, J. of Supercomputing,
Springer book High Performance Computing
in Power and Energy Systems
Elsevier: a book
IET CDT, MDPI Sustainability,
Concurrency and Computation (2 times), Frontiers in Marine Science
Teaching
2019
Fall: CS2323 Computer architecture (100 students)
2019
Spring: CS6490 Hardware architectures for deep learning, ,
CS3523 Operating system (with 1 faculty) and Network security (with 2 faculty)
2018
Fall: CS2323 Computer architecture (121 students)
2018
Spring: Advanced computer architecture, CS3523 Operating system (with 1
faculty) and Network security (with 2 faculty)
2017
Fall: CS2323 (Computer Architecture)
2017
Spring: CS5360 Advanced computer architecture and CS3523 Operating system (with
S. Peri)
2016
Fall: CS2323 Computer Architecture (with A. Franklin) and CS5410 Advanced
memory system architecture
Student Mentoring
Graduate students:
Rujia Wang, University of Pittsburgh,
USA 2016/05-2016/07
Seonglyong Gong, University
of Texas, Austin, USA, 2016/05-2016/08
Matthew (Matt) Poremba,
Penn State University, USA, 2014/06-2014/09
Undergraduate students:
Sai Susmita
(NIT, Trichy), Madhuri Gupta (NIT, Sikkim), Alina Bhutia (NIT, Sikkim), Suparno Ghoshal (Heritage Inst of Tech.)
Technical Skills
Programming Languages/tools: C, C++,
CUDA, Go (from Google), X10 (from IBM), Matlab,
Simulink, System Generator (Xilinx), python, LaTeX, Gnuplot.
Architectural Simulators: Simplescalar, GEMS, Gem5, Sniper, MARSS, GPGPUSim.
Office Address
S-303, ECE Building, IIT Roorkee,
Roorkee, Uttarakhand 247667