| Announcements | Course Outline | General Information | Lectures (Class-wise) | Study Materials |
This is a course of Four (4) credit.
It consists of Three (3) lecture hours per week and One (1) hour tutorial for each of the four sub-batches.
The basic thrust of the course would be to familiarize students with the architecture of a processor and machine level programming.
We will try to stick to the basic course outline as given in Syllabus, but may deviate a bit.
Prerequisite: EC-203 (Digital Electronics) or EC-104 (Digital Logic Design).
The necessary evil (Marks, Examinations, etc.): Class Work Sessional (CWS) = 25%, Mid-Term Exam (MTE) = 25%, End-Term Exam (ETE) = 50%.
CWS will be computed by a weighted sum of different components.
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Introduction to Computer Architecture: Processor Performance, Amdahl's Law |
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Introduction to Instruction Set Architecture (ISA) and Addressing Modes, von Neumann vs. Harvard Architecture, CISC vs. RISC, Instruction Cycle, CPU Performance, CPI |
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Problem Solving on CPU time, Amdahl's Law, etc., Memory Hierarchy |
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Lecture on CPU Structure and Functions by Prof. Padam Kumar |
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Internal registers of CPU, Number representation in Computer, Adder/Subtracter, 1-bit and 32-bit ALU design |
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Designing 32-bit ALU, Increasing its functionality; overflow detection, SLT, Zero, Shifter, Comparator |
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Binary Multiplication, Multiplier design, Booth's algorithm |
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Tutorial-1(for sub-batch CS-2) |
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Binary Division, Floating-Point Number Format, IEEE 754 Standard, Floating-Point Arithmetic |
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Tutorial-1(for sub-batch CS-1) |
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32-bit processor: MIPS ISA, R-type, I-type and J-type instructions, Single Cycle Datapath, Executing R-type and load/store instructions |
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Register file interface, An Example Datapath Design for MIPS ISA |
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MIPS single-cycle datapath revisited with details of micro-operations and control signals |
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Control Unit for single-cycle datapath; Multi-cycle datapath; CPI, CPU clock period and execution time |
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Controller design for multi-cycle datapath |
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Controller design of multi-cycle datapath and introduction to instruction-level pipelining, pipelined datapath |
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Control unit implementation: hardwired and microprogrammed; PLA and ROM |
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Processor control: instruction cycles, microoperations, Control unit design |
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Quiz-1 |
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Microprogrammed control: microinstruction, microprogram (microcode), microPC, vertical and horizontal microprogramming |
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Microprogrammed control: microprogrammed sequencing, Address Select Logic (sequencing logic), microinstruction formats, microinstruction execution, microprogramming |
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Idea of Assembly Language and Machine Language: Role of Compiler and Assembler, Memory addressing, Little and Big Endian forms, 32 register names and purposes of MIPS 32-bit processor, MIPS instruction set, Simple examples of MIPS/assembly code for a C code |
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Class Test-1 |
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Review for Mid-Term Exam, Assignment discussed |
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Mid-Term Examination |
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MIPS ISA and Register Names |
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MIPS ISA and Addressing Modes, Homework given |
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0-, 1-, 2- and 3-address machines, Assembly language programming |
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MIPS assembly language programming, procedure call using stack, QtSPIM simulation tool demo, assembler, linker and loader |
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8-bit Microprocessor: 8085 internal architecture, buses |
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8085 microprocessor architecture, pin configuration, system bus, 8085 registers, control & status signals, T-states, machine cycles, instruction cycles, 8085 ISA, 8085 instruction types and formats, different types of operations, 8085 addressing modes |
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8085: different types of machine cycles and timing diagrams, 8085 interrupts: INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP |
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8085 interrupts, direct memory access (DMA) |
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16-bit microprocessor: 8086 internal architecture, registers, BIU and EU |
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8086 microprocessor: memory segmentation, physical address calculation, addressing modes, instruction set |
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Memory system, RAM, ROM, SRAM vs. DRAM, internal and external memory, memory hierarchy |
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Cache memory concept; Mid-Term Exam scripts shown |
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Cache memory organization, hit, miss, effective access time, Cache memory design issues |
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Cache mapping functions: direct, fully-associative and set-associative caches, replacement and write policies, concept of virtual memory |
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I/O organization, I/O techniques: Programmed I/O, Interrupt-driven I/O, DMA |
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Interrupt I/O Design issues: software poll, daisy chain or hardware poll, multiple interrupts: priorities, Interrupt-driven I/O controller 8259A, Programmable peripheral interface 8255A, DMA controllers |
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Programmable peripheral interface 8255: block diagram and pin layout of 8255, chip select logic and I/O port address, mode selection and control word, DMA controller chip: 8237, Modes of data transfer: parallel and serial, synchronous and asynchronous |
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Discussed list of sections from the chapters of [B6]; An Example of assembly Language Programming for an Accumulator-based processor (Intel 8085) Ref:[B6]; Review of full syllabus for ETE |
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Deadline for submission of group project |
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Class Test-2 (Syllabus: topics covered after MTE) |
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CT-2 scripts shown |
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End-Term Examination (Full Syllabus): 8:45 am - 12:00 noon @ LHC-102 |
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