Publications:

2021:
    Journal:
  1. G. Pahwa, P. Kushwaha, A. Dasgupta, S. Salahuddin and C. Hu, "Compact Modeling of Temperature Effects in Modern MOSFETs down to Cryogenic Temperatures", IEEE Transactions on Electron Devices, 2021.
  2. M.-Y. Kao, Y.-H. Liao, G. Pahwa, A. Dasgupta, S. Salahuddin and C. Hu, "Energy Storage and Reuse in Negative Capacitance", IEEE Transactions on Electron Devices, Vol. 68, Issue 4, Apr. 2021.
  3. Conference:
  4. A. Dasgupta, "Compact Modeling for Gate-All-Around FET Technology", MOS-AK (Asia Pacific) Workshop, 2021.(Invited)
2020:
    Journal:
  1. A. Dasgupta and C. Hu, "Gate-All-Around FET Design Rule for Suppression of Excess Non-linearity ", IEEE Electron Device Letters, Vol. 41, Issue 12, Dec. 2020. (Editor's pick and Cover mention)
  2. A. Dasgupta and C. Hu, "BSIM-CMG compact model for IC CAD: from FinFET to Gate-All-Around FET Technology", Journal of Microelectronic Manufacturing, Vol. 3, 2020. (Invited)
  3. P. Kushwaha, A. Dasgupta, M.-Y. Kao, H. Agarwal, S. Salahuddin, C. Hu, "Design Optimization Techniques in Nanosheet Transistor for RF Applications", IEEE Transactions on Electron Devices, Vol. 67, Issue 10, Oct. 2020.
  4. A. D. Gaidhane, G. Pahwa, A. Dasgupta, A. Verma, and Y. S. Chauhan, "Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport", IEEE Journal of Electron Devices Society, 2020.
  5. M.-Y. Kao, G. Pahwa, A. Dasgupta, S. Salahuddin, C. Hu, "Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET", IEEE Transactions on Electron Devices, Vol. 67, Issue 10, October 2020.
  6. M.-Y. Kao, H. Agarwal, Y.-H. Liao, S. Cheema, A. Dasgupta, P. Kushwaha, A. Tan, S. Salahuddin, C. Hu, "Negative Capacitance Enables FinFET Scaling Beyond 3nm Node", arXiv:2007.14448 [physics.app-ph], July 2020.
  7. C. K. Dabhi, S. S. Parihar, A. Dasgupta, and Y. S. Chauhan, "Compact Model of Negative-Capacitance FDSOI FETs for Circuit Simulations", IEEE Transactions on Electron Devices, Vol. 67, Issue 7, May 2020.
  8. A. Dasgupta, S. S. Parihar, H. Agarwal, P. Kushwaha, Y. S. Chauhan and C. Hu, "Compact Model for Geometry Dependent Mobility in Nanosheet FETs", IEEE Electron Device Letters, Vol. 41, Issue 3, March 2020.
  9. A. Dasgupta, S. S. Parihar, P. Kushwaha, H. Agarwal, M.-Y. Kao, S. Salahuddin, Y. S. Chauhan and C. Hu, "BSIM Compact Model for Quantum Confinement in Advanced Nanosheet FETs", IEEE Transactions on Electron Devices, Vol. 67, Issue 2, Feb. 2020.
  10. Conference:
  11. A. D. Gaidhane, G. Pahwa, A. Dasgupta, A. Verma and Y. S. Chauhan, "Compact Modeling of Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020.
  12. H. Agarwal, P. Kushwaha, A. Dasgupta, M.-Y. Kao, T. Morshed, G. Workman, K. Shanbhag, X. Li, Y. S. Chauhan, S. Salahuddin and C. Hu,, "BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel Inversion", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020.
2019:
    Journal:
  1. Y.-K. Lin, H. Agarwal, M.-Y. Kao, Z. Zhou, Y. H. Liao, A. Dasgupta, P. Kushwaha, S. Salahuddin, and C. Hu, "Spacer Engineering in Negative Capacitance FinFETs", IEEE Electron Device Letters, Vol. 40, Issue 6, June 2019.
  2. P. Kushwaha, H. Agarwal, A. Dasgupta, M.-Y. Kao, Y. Lu, Y. Yue, X. Chen, J. Wang, W. Sy, F. Yang, PR. C. Chidambaram, S. Salahuddin, and C. Hu, "Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology node", IEEE Electron Device Letters, Vol. 40, Issue 6, June 2019.
  3. M.-Y. Kao, Y.-K. Lin, H. Agarwal, Y.-H. Liao, P. Kushwaha, A. Dasgupta, S. Salahuddin, and C. Hu, "Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly along the Channel", IEEE Electron Device Letters, Vol. 40, issue 5, May 2019.
  4. H. Agarwal, P. Kushwaha, Y.-K. Lin, M.-Y. Kao, Y.-H. Liao, A. Dasgupta, S. Salahuddin, and C. Hu, "Proposal for Capacitance Matching in Negative Capacitance Field Effect Transistors", IEEE Electron Device Letters, Vol. 40, Issue 3, March 2019. (EDL cover page)
  5. A. Dasgupta, A. Verma, and Y. S. Chauhan, "Analysis and Compact Modeling of Insulator-Metal-Transition Material based PhaseFET Including Hysteresis and Multi-domain Switching", IEEE Transactions on Electron Devices, Vol. 66, Issue 1, Jan. 2019.
  6. Conference:
  7. P. Kushwaha, H. Agarwal, A. Dasgupta, Y. K. Lin, M-Y. Kao, Y. S. Chauhan, S. Salahuddin and C. Hu, "Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET", IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, USA, Oct. 2019.
2018:
    Journal:
  1. C. K. Dabhi, A. Dasgupta, P. Kushwaha, H. Agarwal, C. Hu, and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise including Back Bias Effect in FD-SOI MOSFET", IEEE Microwave and Wireless Components Letters, Vol. 28, Issue 7, July 2018.
  2. A. Dasgupta, P. Rastogi, A. Agarwal, C. Hu, and Y. S. Chauhan, "Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition", IEEE Transactions on Electron Devices, Vol. 65, Issue 3, March 2018.
  3. Conference:
  4. A. Dasgupta, P. Rastogi, D. Saha, A. Gaidhane, A. Agarwal and Y. S. Chauhan, "Modeling of Multi-domain Switching in Ferroelectric Materials: Application to Negative Capacitance FETs", IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 2018.
  5. D. K. Singh, A. Dasgupta, A. Agarwal and Y. S. Chauhan, "Incident Flux based Monte Carlo simulation of Silicon and GaAs FETs in Quasi-ballistic regime", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, India, Dec. 2018.
  6. P. Rastogi, A. Dasgupta, and Y. S. Chauhan, "Diameter Scaling in III-V Gate-All-Around Transistor for Different Cross-Sections", IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, Mar. 2018. (Best Paper Award)
  7. Y. S. Chauhan, C. Yadav, A. Dasgupta, and P. Rastogi, "Atomistic Simulation and Compact Modeling of Atomically Thin Transistors", IEEE International Conference on Electronics and Computer Engineering (ICECE), Dhaka, Bangladesh, Dec. 2018. (Invited)
  8. Thesis:
  9. A. Dasgupta, "Compact Modeling of Electrostatics, Quasi-ballistic Transport and Noise in MOSFETs and Magnetic Tunnel Junctions", Ph.D. Thesis, Feb. 2018.
2017:
    Journal:
  1. Y. Sahu, P. Kushwaha, A. Dasgupta, C. Hu, and Y. S. Chauhan, "Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect", IEEE Transactions on Microwave Theory and Techniques, Vol. 65, Issue 7, Jul. 2017.
  2. A. Dasgupta, A. Agarwal, and, Y. S. Chauhan, "An Improved Model for Quasi-Ballistic Transport in MOSFETs", IEEE Transactions on Electron Devices, Vol. 64, Issue 7, Jul. 2017.
  3. A. Dasgupta, A. Agarwal, and, Y. S. Chauhan, "Unified Compact Model for Nanowire Transistors including Quantum Effects and Quasi-ballistic Transport", IEEE Transactions on Electron Devices, Vol. 64, Issue 4, Apr. 2017.
  4. Conference:
  5. D. Datta, H. Dixit, S. Agarwal, A. Dasgupta, M. Tran, D. Houssameddine, Y. S. Chauhan, D. Shum, and F. Benistant, "Quantitative Model for Switching Asymmetry in Perpendicular MTJ: A Material-Device-Circuit Co-Design", IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 2017.
  6. A. Dasgupta and Y. S. Chauhan, "Modeling of Flicker Noise in Quasi-ballistic FETs", IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, Japan, Sep. 2017.
  7. A. Dasgupta, C. Gupta, A. Dutta, Y.-K. Lin, S. Srihari, T. Ethirajan, C. Hu, and Y. S. Chauhan, "Modeling of Body-bias Dependence of Overlap Capacitances in Bulk MOSFETs", IEEE International Conference on VLSI Design, Hyderabad, India, Jan. 2017.
2016:
    Journal:
  1. A. Dasgupta, A. Agarwal, Sourabh Khandelwal and, Y. S. Chauhan, "Compact Modeling of Surface Potential, Charge and Current in Nanoscale Transistors under Quasi-Ballistic Regime", IEEE Transactions on Electron Devices, Vol. 63, Issue 11, Nov. 2016.
  2. P. Kushwaha, A. Dasgupta, Y. Sahu, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Characterization of RF Noise in UTBB FD-SOI MOSFET", IEEE Journal of the Electron Devices Society, Vol. 4, Issue 6, Nov. 2016.
  3. A. Dasgupta and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise in HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 26, Issue 6, June 2016.
  4. S. A. Ahsan, S. Ghosh, A. Dasgupta, K. Sharma, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling in Dual Field Plate Power GaN HEMT for Accurate Switching Behaviour", IEEE Transactions on Electron Devices, Vol. 63, Issue 2, Feb. 2016.
  5. Conference:
  6. S. Ghosh, S. A. Ahsan, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "GaN HEMT Modeling for Power and RF Applications using ASM-HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
  7. D. K. Singh, A. Dasgupta, and Y. S. Chauhan, "Accurate Modeling of Centroid Shift in III-V FETs including Non-linear Potential Profile and Wave-function Penetration", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
  8. S. Ghosh, A. Dasgupta, A. K. Dutta, S. Khandelwal, and Y. S. Chauhan, "Physics based Modeling of Gate Current including Fowler-Nordheim Tunneling in GaN HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
  9. A. Dasgupta, H. Agarwal, A. Agarwal, and Y. S. Chauhan, "Modeling of Flicker Noise in Quasi-ballistic devices", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
  10. C. K. Dabhi, A. Dasgupta, and Y. S. Chauhan, "Computationally efficient Analytical Surface Potential model for UTBB FD-SOI Transistors", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
  11. C. K. Dabhi, P. Kushwaha, A. Dasgupta, H. Agarwal, and Y. S. Chauhan, "Impact of Back Plane Doping on RF Performance of FD-SOI Transistor using Industry Standard BSIM-IMG Model", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
  12. A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, N. Defrance, and Y. S. Chauhan, "Modeling DC, RF and Noise behavior of GaN HEMTs using ASM-HEMT Compact Model", IEEE International Microwave and RF Conference (IMaRC), Delhi, India, Dec. 2016.
  13. S. A. Ahsan, S. Ghosh, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Advanced SPICE Model for Gallium Nitride High Electron Mobility Transistors", International Conference of Young Researchers on Advanced Materials (ICYRAM), Bangalore, India, Dec. 2016.
2015:
    Journal:
  1. A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Surface potential based Modeling of Thermal Noise for HEMT circuit simulation", IEEE Microwave and Wireless Components Letters, Vol. 25, Issue 6, June 2015.
  2. S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2, Feb. 2015.
  3. Conference:
  4. S. Agnihotri, S. Ghosh, A. Dasgupta, A. Ahsan, S. Khandewal, and Y. S. Chauhan, "Modeling of Trapping Effects in GaN HEMTs", IEEE India Conference (INDICON), New Delhi, India, Dec. 2015.
  5. A. Dasgupta, A. Agarwal, and Y. S. Chauhan, "Compact Model for charge centroid in III-V FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  6. K. Sharma, S. Ghosh, A. Dasgupta, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Capacitance Analysis of Field Plated GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  7. A. Dasgupta, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Quasi-Ballistic transport in FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  8. J. P. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta, and Y. S. Chauhan "BSIM-CMG: Standard FinFET Compact Model for Advanced Circuit Design", IEEE European Solid-State Circuit Conference (ESSCIRC), Graz, Austria, Sept. 2015. (Invited)
  9. S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling of a GaN HEMT with Gate and Source Field Plates", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.
  10. A. Dasgupta and Y. S. Chauhan, "Surface Potential Based Modeling of Induced Gate Thermal Noise for HEMTs", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.
  11. A. Dasgupta, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Compact model for GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.
  12. K. Sharma, A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Effect of Access Region and Field Plate on Capacitance behavior of GaN HEMT", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.
2014:
    Journal:
  1. A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Compact Modeling of Flicker Noise in HEMTs", IEEE Journal of the Electron Devices Society, Vol. 2, Issue 6, Nov. 2014.
  2. Conference:
  3. A. Dasgupta, C. Yadav, P. Rastogi, A. Agarwal, and Y. S. Chauhan, "Analysis and Modeling of Quantum Capacitance in III-V Transistors", IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014. (Best Poster Award)
  4. S. Khandelwal, T. A. Fjeldly, Y. S. Chauhan, B. Iniguez, S. Ghosh, A. Dasgupta, K. Sharma, "ASM-HEMT Model: A Physics-based Compact Model for GaN HEMTs", MOS-AK Workshop, Berkeley, USA, Dec. 2014.
  5. Thesis:
  6. A. Dasgupta, "Noise modeling in High Electron Mobility Transistors", M.Tech Thesis, May. 2014.
2013:
  1. S. Agnihotri, S. Ghosh, A. Dasgupta, S. Khandewal, and Y. S. Chauhan, "A Surface Potential based Model for GaN HEMTs", IEEE PrimeAsia, Visakhapatnam, Dec. 2013. (Gold Leaf Certificate)
 
 
 

Invited presentations/talks:

  1. A. Dasgupta, "Compact Modeling for Gate-All-Around FET Technology", MOS-AK (Asia Pacific) Workshop, Feb. 2021.
  2. A. Dasgupta, "Design and Modeling of Nanosheet FETs", IITK Short Course, Feb. 2021.
  3. A. Dasgupta, "Design Considerations and Compact Modeling of GAAFETs for Upcoming Technology Nodes", AICTE Workshop, NIT Meghalaya, Feb. 2021.(Keynote)
  4. A. Dasgupta, "Compact Modeling of STT-MRAMs", BDMC webinar, Oct. 2020.
  5. A. Dasgupta, "Compact modeling of Nanosheet FETs", BDMC webinar, Sept. 2019.